The fabrication of semiconductor devices including floating gate arrays involves many complex steps. These steps can include a Poly 1 Array step that involves depositing a nitride layer over the silicon wafer, patterning the nitride layer with a photolithographic process, and etching the nitride layer. The silicon wafer can then be placed into a furnace where a plurality of field oxide isolation structures (i.e., thick field regions) are grown on the silicon wafer. The formation of the field oxide isolation structures in this manner results in a field oxide isolation structures that extend above the plane of the silicon wafer. A layer of polysilicon is then deposited over the silicon wafer and the multiple thick field oxide regions.
In completing the Poly 1 Array step, conventional manufacturing methods include a pattern level step that involves putting down a layer of photoresist on the polysilicon and exposing a reticle onto the photoresist to define a pattern. The reticle can consist of a pattern of chrome and glass, that when projected onto the photoresist, defines what areas of the photoresist will be exposed to light. A stepper then exposes the photoresist while the reticle acts as a mask, resulting in a pattern on the silicon wafer. The pattern will leave photoresist over the polysilicon in the channel areas between the field oxide isolation structures and will remove the photoresist over the polysilicon on the raised portions of the field oxide isolation structures.
In order to create the proper pattern on the wafer, the reticle must be properly aligned. To align the reticle, alignment marks can be placed at predetermined locations on a variety of previous pattern levels. The stepper can read the alignment marks and use them to properly align the reticle with the wafer. The reticle is then exposed and the pattern is formed.
A polysilicon etch is then applied that will remove the polysilicon layer not covered by photoresist, but will not remove the photoresist (and thus, will not remove the polysilicon covered by the photoresist). A photoresist etch is then applied to remove the remaining photoresist. The finished product resulting from this Poly 1 Array process consists of a silicon wafer with raised field oxide isolation structures where the tops of the field oxide isolation structures are exposed and the channels between the field oxide isolation structures are covered by a plurality of polysilicon layers. These polysilicon layers between the thick field regions provide the structure used to manufacture floating gate arrays on the silicon wafer.
This conventional method for forming floating gate array regions (the Poly 1 Array step) including a pattern level step can increase manufacturing delays and costs. The pattern level step requires the use of stepper machines that are expensive and typically exist in limited numbers. The pattern level step also requires an alignment procedure to align the reticle on the silicon wafer. This alignment procedure has inherent inaccuracies. Both the pattern level and the alignment procedures represent additional manufacturing steps when forming floating gate array regions in the wafer.
This conventional method of creating floating gate regions on a silicon wafer can also experience uniformity problems across the die during manufacture due to variations in light effects and chemical etch composition at the edge of a wafer. Furthermore, conventional methods can also produce post-etch filaments that can cross between field oxide isolation structures and cause shorts between devices.